Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

被引：71

作者：

Liu, Xi ^{[1
]}

Chen, Qiao ^{[2
]}

Sundaram, Venkatesh ^{[3
]}

Tummala, Rao R. ^{[2
,3
]}

Sitaraman, Suresh K. ^{[1
]}

机构：

[1] Georgia Inst Technol, George W Woodruff Sch Mech Engn, Atlanta, GA 30332 USA

[2] Georgia Inst Technol, Sch Mat Sci & Engn, Atlanta, GA 30332 USA

[3] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

MICROELECTRONICS RELIABILITY | 2013年 / 53卷 / 01期

关键词：

RELIABILITY; TSV; CHIP; CU;

D O I：

10.1016/j.microrel.2012.06.140

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Through-silicon vias (TSVs), being one of the key enabling technologies for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and even less experimental failure analysis has been reported in the literatures. In this paper, TSV samples have been fabricated and tested under thermal-shock test from -55 degrees C to 125 degrees C. Various experimental techniques have been used to carry out the failure mechanism analysis. Both Cu/SiO2 interfacial separations and SiO2/Si cohesive cracking were identified at various locations along the Cu/SiO2/Si interfaces. Finite-element based fracture analysis models have also been developed to understand the interfacial/cohesive crack initiation and propagation. A centered finite difference approach (CFDA) based on Griffith's energy balance has been developed for the axisymmetric crack propagation analysis. Also, the virtual crack closure technique (VCCT) has been applied for the axisymmetric interfacial/cohesive crack analysis. Both methods match perfectly with each other for linear elastic analysis, and agree well for elastic-plastic analysis. The fracture analysis results match the experimental observations, and also provide insight on the reason behind different failure mechanisms. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：70 / 78

页数：9

共 22 条

[1] Characterization of chip scale packaging materials [J].

Amagai, M .

MICROELECTRONICS RELIABILITY, 1999, 39 (09) :1365-1377

[2] TSV Stress Testing and Modeling [J].

Amagai, Masazumi ;

Suzuki, Yutaka .

2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, :1273-1280

[3]

Anderson TL, 2004, FRACT MECH FUNDAMENT

[4] Measurements of the debond energy for thin metallization lines on dielectrics [J].

Bagchi, A ;

Evans, AG .

THIN SOLID FILMS, 1996, 286 (1-2) :203-212

[5] Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits [J].

Budiman, A. S. ;

Shin, H. -A. -S. ;

Kim, B. -J. ;

Hwang, S. -H. ;

Son, H. -Y. ;

Suh, M. -S. ;

Chung, Q. -H. ;

Byun, K. -Y. ;

Tamura, N. ;

Kunz, M. ;

Joo, Y. -C. .

MICROELECTRONICS RELIABILITY, 2012, 52 (03) :530-533

[6]

Chapra S.C., 1998, NUMERICAL METHODS EN, V3rd

[7] Cu pumping in TSVs: Effect of pre-CMP thermal budget [J].

De Wolf, I. ;

Croes, K. ;

Pedreira, O. Varela ;

Labie, R. ;

Redolfi, A. ;

Van De Peer, M. ;

Vanstreels, K. ;

Okoro, C. ;

Vandevelde, B. ;

Beynea, E. .

MICROELECTRONICS RELIABILITY, 2011, 51 (9-11) :1856-1859

[8] Numerical and Experimental Investigation of Thermomechanical Deformation in High-Aspect-Ratio Electroplated Through-Silicon Vias [J].

Dixit, Pradeep ;

Yaofeng, Sun ;

Miao, Jianmin ;

Pang, John H. L. ;

Chatterjee, Ritwik ;

Tummalaa, Rao R. .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2008, 155 (12) :H981-H986

[9]

IANNUZZELLI R, 1991, 1991 PROCEEDINGS : 41ST ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, P410, DOI 10.1109/ECTC.1991.163908

[10]

Jung MG, 2011, ICCAD-IEEE ACM INT, P563, DOI 10.1109/ICCAD.2011.6105386

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