Design of a 12-Bit SAR ADC for Neural Signal Acquisition
被引:0
作者:
Yang, Hai-Dong
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机构:
Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R ChinaBeijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China
Yang, Hai-Dong
[1
]
Li, Xiao-Ran
论文数: 0引用数: 0
h-index: 0
机构:
Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R ChinaBeijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China
Li, Xiao-Ran
[1
]
Wang, Xing-Hua
论文数: 0引用数: 0
h-index: 0
机构:
Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R ChinaBeijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China
Wang, Xing-Hua
[1
]
机构:
[1] Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China
来源:
MECHANICS AND MATERIALS SCIENCE
|
2018年
关键词:
SAR ADC;
Calibration Circuit;
Sectional Capacitor Array;
D O I:
暂无
中图分类号:
TH [机械、仪表工业];
学科分类号:
0802 ;
摘要:
This paper presents a 12-bits differential successive approximation register ADC (SAR ADC). A calibration circuit is added to improve the accuracy reduction caused by mismatch. And a segmented capacitor array cascaded with a resister-string is adopted to reduce the layout area. The whole circuit design and layout are completed in this paper. The ADC occupies 0.54mm2 in a SMIC180nm technology and operates at 1.8V supply. The simulation results show that the Effective Number of Bits (ENOB) is 11.1 bits, the Signal to Noise and Distortion Ratio (SNDR) is 68.8dB and the Spurious Free Dynamic Range (SFDR) is 74.2dB for an input signal of 10 kHz and 1.2V peak-to-peak voltage with the clock frequency is 6.4MHz..