Delay hazards in complex gate based speed independent VLSI circuits

被引：1

作者：

Tabrizi, N ^{[1
]}

Liebelt, MJ ^{[1
]}

Eshraghian, K ^{[1
]}

机构：

[1] UNIV ADELAIDE,DEPT ELECT & ELECTR ENGN,ADELAIDE,SA 5005,AUSTRALIA

来源：

SIXTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1996年

关键词：

asynchronous circuits; hazards; isochronic forks; signal transition graphs (STGs); speed independent circuits (SICs);

D O I：

10.1109/GLSV.1996.497631

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：266 / 271

页数：6

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