A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs

被引：0

作者：

Konishi, Tomoaki ^{[1
]}

Yotsuyanagi, Hiroyuki ^{[1
]}

Hashizume, Masaki ^{[1
]}

机构：

[1] Univ Tokushima, Inst Sci & Technol, Tokushima 7708506, Japan

来源：

2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz.

引用

页数：6

共 14 条

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