Control and data acquisition ATCA/AXIe board designed for high system availability and reliability of nuclear fusion experiments

被引：8

作者：

Batista, A. J. N. ^{[1
]}

Leong, C. ^{[2
]}

Bexiga, V. ^{[2
]}

Rodrigues, A. P. ^{[1
]}

Combo, A. ^{[1
]}

Carvalho, B. B. ^{[1
]}

Carvalho, P. F. ^{[1
]}

Fortunato, J. ^{[1
]}

Santos, B. ^{[1
]}

Carvalho, P. ^{[1
]}

Correia, M. ^{[1
]}

Teixeira, J. P. ^{[2
]}

Teixeira, I. C. ^{[2
]}

Sousa, J. ^{[1
]}

Goncalves, B. ^{[1
]}

Varandas, C. A. F. ^{[1
]}

机构：

[1] Univ Tecn Lisboa, Inst Super Tecn, Inst Plasmas & Fusao Nucl, P-1049001 Lisbon, Portugal

[2] INESC ID, Lisbon, Portugal

来源：

FUSION ENGINEERING AND DESIGN | 2013年 / 88卷 / 6-8期

关键词：

Fast control; Data acquisition; PCI express; FPGA; ATCA; AXIe;

D O I：

10.1016/j.fusengdes.2013.01.093

中图分类号：

TL [原子能技术]; O571 [原子核物理学];

学科分类号：

0827 ; 082701 ;

摘要：

This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (10) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Management Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, point-to-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi-Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog 10 channels with galvanic isolation and an optional signal chopper mode, for offset compensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code. (C) 2013 Elsevier B.V. All rights reserved.

引用

页码：1332 / 1337

页数：6

共 4 条

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