Development of a front-end ASIC for silicon -strip detectors of the J-PARC muon g? 2 /EDM experiment

被引：4

作者：

Sato, Yutaro ^{[1
]}

Fujita, Yowichi ^{[1
]}

Hamada, Eitaro ^{[1
]}

Kishishita, Tetsuichi ^{[1
]}

Mibe, Tsutomu ^{[1
]}

Sasaki, Osamu ^{[1
]}

Shoji, Masayoshi ^{[1
]}

Suehara, Taikan ^{[2
]}

Tanaka, Manobu ^{[1
]}

Tojo, Junji ^{[2
]}

Tsutsumi, Tuki ^{[2
]}

Yamanaka, Takashi ^{[2
]}

Yoshioka, Tamaki ^{[2
]}

机构：

[1] High Energy Accelerator Res Org, Tsukuba, Ibaraki, Japan

[2] Kyushu Univ, Fukuoka, Japan

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 2020年 / 969卷

关键词：

Front-end electronics; g−2; J-PARC; muon; Silicon-strip detector;

D O I：

10.1016/j.nima.2020.164035

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B. © 2020 Elsevier B.V.

引用

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