Modeling Single Event Transients in Advanced Devices and ICs

The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.