A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design

被引：0
|
作者：
Xia, Bingbing [1 ]
Qiao, Fei [1 ]
Yang, Huazhong [1 ]
Wang, Hui [1 ]
机构：
[1] Tsinghua Univ, Tsinghua Natl Lab Informat Sci & Technol, Inst Circuits & Syst, Dept Elect Engn, Beijing, Peoples R China
来源：
PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010) | 2010年
基金：
中国国家自然科学基金;
关键词：
Fault-tolerant; Hardware-software Co-design; Multi-core;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional software redundancy (time redundant). Therefore, it will be a good choice for the fault-tolerant architecture for the future high-reliable multi-core systems.
引用
收藏
页码：191 / 197
页数：7
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