Digital Background Calibration for pipelined ADC and Implementation of Full FPGA Verification Platform

被引：0

作者：

Zhu, Yi-Long ^{[1
]}

Yin, Yong-Sheng ^{[1
]}

Wang, Ming ^{[1
]}

Ni, Wei ^{[1
]}

机构：

[1] Hefei Univ Technol, Inst VLSI Design, Hefei, Peoples R China

来源：

2012 5TH INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING (CISP) | 2012年

关键词：

pipelined ADC; digital background calibration; split-ADC; pseudorandom sequence; capacitor mismatch; finite opamp dc gain; SPLIT ADC; ARCHITECTURE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The convergence speed is an important indicator of the digital background calibration technique for pipelined ADC. A Split-ADC architecture is used to calibrate the error resulting from capacitor mismatches and finite opamp dc gain in this work. Two channel ADCs, one with equivalent 1% interstage gain error in the first stage and the other with 2%, compose the "split ADCs" which are implemented on a FPGA chip. Simulation results show the interstage gain will converge in approximately 105 conversions and the interstage gain curve become smoother. With calibration, SFDR enhances from 79.4dB dB to 93.7dB and SNDR enhances from 58.9dB to 81.6dB.

引用

页码：1435 / 1438

页数：4

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