Design of a Multi-rate Quasi-Cyclic Low-Density Parity-Check Encoder based on Pipelined Rotate-Left-Accumulator Circuits

被引：0
作者：
Wang, Fei [1 ]
Zhang, Peng [1 ]
Wan, Xin [2 ]
Liu, Jin [2 ]
机构：
[1] Commun Univ China, Sch Informat Engn, Beijing, Peoples R China
[2] Commun Univ China, Engn Ctr Digital Audio & Video, Beijing, Peoples R China
来源：
2014 7TH INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING (CISP 2014) | 2014年
关键词：
QC-LDPC; Encoder; Rotate-Left-Accumulator(RLA); DTMB; FPGA; SHANNON LIMIT; CODES;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A serial-input serial-output encoder based on pipelined rotate-left-accumulator (RLA) circuits is designed for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Chinese digital terrestrial/television multimedia broadcasting (DTMB) standard. The RLA circuit can make the area usage economical, and the pipelined architecture can simplify the memory structure. The encoder is implemented on FPGA. Simulation results demonstrate that the design meets the requirement of DTMB standard with lower energy consumption and fewer hardware resources.
引用
收藏
页码：1105 / 1109
页数：5
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