A custom digital intermediate frequency filter for the American mobile telephone system

被引:8
作者
Nilsson, P
Torkelson, M
机构
[1] Department of Applied Electronics, University of Lund
[2] Lund Institute of Technology, Lund University, Lund
[3] Department of Applied Electronics, Lund University, Lund
[4] ETH, Zürich
[5] Lund University, Lund
[6] University of California, Berkeley, CA
[7] Department of Applied Electronics, Lund University
[8] Ericsson Radio Systems, Stockholm
关键词
application specific integrated circuits; bandpass filters; bit-serial arithmetic; bit-serial design; clocks; CMOS digital integrated circuits; digital communication; digital filters; digital signal processors; fixed coefficient arithmetic; fixed point arithmetic; heterodyne receivers; IF filters; IIR digital filters; land mobile radio cellular systems; lattice filters; layout of integrated circuits; multiplying circuits; very-large-scale integration; wave digital filters;
D O I
10.1109/4.585254
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A digital filter for Intermediate frequency filtering in mobile communication systems is presented. The purpose of the work is to show an alternative to the analog filters which are used in most of today's heterodyne receivers. Bit-serial arithmetic is applied on a twelfth-order wave digital lattice filter algorithm, The paper also shows a method for retiming such algorithms. In the paper, the power consumption in two fabricated prototypes are compared, By customizing the library cells, the power consumption has been reduced significantly, In the low power prototype, the power dissipation is 8 mW using 3 V supply voltage. The prototype is a 10 MIPS design fabricated in a 0.8-mu m standard two-metal-layer CMOS process.
引用
收藏
页码:806 / 815
页数:10
相关论文
共 31 条
[1]  
ADACHI T, 1994, PROCEEDINGS OF THE IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE, P159, DOI 10.1109/CICC.1994.379746
[2]   A UNIFIED SINGLE-PHASE CLOCKING SCHEME FOR VLSI SYSTEMS [J].
AFGHAHI, M ;
SVENSSON, C .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) :225-233
[3]  
Bakoglu H., 1990, CIRCUITS INTERCONNEC
[4]   METHOD FOR TIMING RECOVERY IN PRESENCE OF MULTIPATH DELAY AND COCHANNEL INTERFERENCE [J].
BRANDAO, AL ;
LOPES, LB ;
MCLERNON, DC .
ELECTRONICS LETTERS, 1994, 30 (13) :1028-1029
[5]   A LOW-POWER, AREA-EFFICIENT DIGITAL-FILTER FOR DECIMATION AND INTERPOLATION [J].
BRANDT, BP ;
WOOLEY, BA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (06) :679-687
[6]  
Brange Lars, 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference, P72
[7]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[8]   DESIGNING ON-CHIP CLOCK GENERATORS [J].
CHEN, DL .
IEEE CIRCUITS AND DEVICES MAGAZINE, 1992, 8 (04) :32-36
[9]   A LOW-POWER 12-B ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP PRECISION TRIMMING [J].
DEWIT, M ;
TAN, KS ;
HESTER, RK .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :455-461
[10]  
*EL IND ASS, 1989, 54 EL IND ASS