Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-high-speed caches, decoding delay is a key element to consider when selecting an SEC code. Single error correction orthogonal Latin square (SEC OLS) codes have the fastest decoding method. However, these codes impose a higher number of parity check bits compared to other SEC codes. These extra parity bits need to be stored with each data word in cache data array, which increased cache overheads. This may limit their adoption only to applications that can handle such overheads. In this paper, a modified SEC OLS coding scheme is proposed to reduce the number of stored parity check bits. Compared to the original SEC OLS codes, the proposed coding scheme reduces 25% and 31.3% of the stored parity bits when implemented to protect 16-bit and 64-bit data words, respectively. The results of FPGA and ASIC simulation and synthesis show that using the modified SEC to protect 16-bit words can be an attractive solution because it saves a significant amount of parities storage area, while running at a speed comparable to the original SEC OLS code. The implementation of the proposed SEC code to protect 64-bit words may still be suitable for area-sensitive cache applications that can cope with the slightly increased decoding delay.