Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs

Technology scaling has led FPGA manufactures to produce FPGAs with millions of logic cells. It has motivated hardware designers to map increasingly large applications into FPGAs. However, state-of-the-art FPGA CAD tools consume longer runtime to compile such applications affecting the design productivity. Modular design methodology, which allows to partition a large application into smaller modules, compile and verify individually and subsequently combine all modules to get the final design, has been introduced in the past to improve the design productivity. To reduce the dominant power dissipation component in FPGAs, the routing power, existing workflows have considered data communication between design modules during module formation, as well as during placing them on FPGA space in the final solution. But, these workflows have not discussed a methodology to select the best shape and the region (footprint) on FPGA space for each module. Selecting proper footprints, on the other hand, is becoming a critical process on modern FPGAs because of their heterogeneity in resources and column arrangement. In this work we propose a communication-aware module placement strategy which selects the best footprint for each module. Our methodology has shown about 16% routing power reduction with respect to commercial CAD flow and about 11% with respect to a communication-aware design partitioning workflow that does not consider placement of modules on FPGA.