A fully integrated SONET OC-48 transceiver in standard CMOS

被引：21

作者：

Momtaz, A ^{[1
]}

Cao, J

Caresosa, M

Hairapetian, A

Chung, D

Vakilian, K

Green, M

Tan, WG

Jen, KC

Fujimori, I

Cai, YJ

机构：

[1] Broadcom Corp, Opt Transport Grp, Irvine, CA 92618 USA

[2] Univ Calif Irvine, Dept Elect & Comp Engn, Irvine, CA 92697 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 12期

关键词：

broadband communication; mixed analog-digital integrated circuits; optical fiber communication; phase-locked loops; phase noise; SONET; TR devices;

D O I：

10.1109/4.972147

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-mum CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.

引用

页码：1964 / 1973

页数：10

共 6 条

[1] GU R, 1999, ISSCC FEB, P352
[2] 2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48)
Gutierrez, G
Kong, SA
[J]. IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 575 - 578
[3] A general theory of phase noise in electrical oscillators
Hajimiri, A
Lee, TH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (02) : 179 - 194
[4] A VARIABLE DELAY-LINE PLL FOR CPU - COPROCESSOR SYNCHRONIZATION
JOHNSON, MG
HUDSON, EL
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) : 1218 - 1223
[5] Peterson W. W., 1972, ERROR CORRECTING COD
[6] [No title captured]

← 1 →