Reliability Monitoring of Digital Circuits by in situ Timing Measurement

被引：0

作者：

Aryan, Nasim Pour ^{[1
]}

Georgakos, Georg ^{[2
]}

Schmitt-Landsiedel, Doris ^{[1
]}

机构：

[1] Tech Univ Munich, D-80290 Munich, Germany

[2] Infineon Technol AG, Y Neubiberg, Germany

来源：

2013 23RD INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.

引用

页码：150 / 156

页数：7

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