Asymmetric SEU in SOISRAMs

被引：4

作者：

McMarr, PJ

Nelson, ME

Liu, ST

Nelson, D

Delikat, KJ

Gouker, P

Tyrrell, B

Hughes, H

机构：

[1] USN, Res Lab, Washington, DC 20375 USA

[2] USN Acad, Engn & Weapons Div, Annapolis, MD 21402 USA

[3] Honeywell Def & Space Elect Syst, Plymouth, MN 55441 USA

[4] MIT, Lincoln Lab, Lexington, MA 02420 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2005年 / 52卷 / 06期

关键词：

random access memories; silicon-on-insulator technology; single event upset; SINGLE-EVENT UPSETS; CHARGE COLLECTION; SOI TECHNOLOGIES; N-TYPE; NEUTRON; NUCLEAR; SIMULATION; CIRCUITS; PROTONS; PHYSICS;

D O I：

10.1109/TNS.2005.860720

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Partially depleted (PD) 0.15 mu m CMOS silicon-on-insulator (SOI) SRAMs were exposed to heavy ions, 14 MeV neutrons, and protons. The upset threshold and saturated cross section LET values were determined from heavy ion exposures. The SRAMs were then exposed at various angles of incidence with respect to a 14 MeV neutron source to a total fluence of 4 x 10(13) n/cm(2). The number of upsets from front exposure was more than double the number from back exposure. Following neutron exposure, proton upset measurements were performed. For a given fluence, the number of proton induced upsets was essentially identical to the number of neutron induced upsets.

引用

页码：2481 / 2486

页数：6

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