Image Processing VLSI Architecture Based on Data Compression

被引：0

作者：

Hariyama, Masanori ^{[1
]}

Yoshida, Hisashi ^{[1
]}

Kameyama, Michitaka ^{[1
]}

Kobayashi, Yasubiro ^{[2
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Aoba 6-6-05, Sendai, Miyagi 9808579, Japan

[2] Oyama Natl Coll Technol, Oyama, Tochigi 3230806, Japan

来源：

2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To design low-power and high-speed image processors, the reduction of the number of interconnection units plays an important role. This paper presents a data-compression-based VLSI architecture that reduces the number of interconnection units between processing elements and memory modules without performance degradation. For example of a stereo matching VLSI, the number of interconnection units is reduced to 75%. The signal transition, which directly affects the dynamic power for data transfer, is also reduced to 50%.

引用

页码：430 / +

页数：2