Design of interleavers for turbo codes: Iterative interleaver growth algorithms of polynomial complexity

This paper addresses the problem of designing interleavers for parallel concatenated convolutional codes (PCCC's) tailored to specific constituent codes. We start by establishing the role of the interleaver in the PCCC and the various parameters that influence the performance of the PCCC with a given interleaver, Subsequently, we define a canonical form of the interleaving engine denoted as the finite-state pc rmuter (FSP) and demonstrate the minimal delay property of this canonical form, For any given permutation, we present a procedure for deriving the canonical FSP engine, We address the issue of implementation of the FSP and propose a very simple structure for the FSP, Next, using the structural property of the FSP engine, we develop a systematic iterative technique for construction of interleavers with a complexity that is polynomial in the interleaver size. Subsequently, we develop a cost function that, coupled with the iterative interleaver growth procedure, can be used to design optimized interleavers for PCCC's, We provide examples of application of the interleaver design technique, and compare the designed interleavers with some of the interleavers of comparable size found in the literature.