Dynamic Power Optimization of LFSR Using Clock Gating

被引：0
|
作者：
Madhushree, K. [1 ]
Rajan, Niju [2 ]
机构：
[1] NMAM Inst Technol, VLSI Design & Embedded Syst, Nitte, Karkala, India
[2] NMAM Inst Technol, Dept ECE, Nitte, Karkala, India
来源：
2017 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS) | 2017年
关键词：
Clock Gating; Linear Feedback Shift Register; Dynamic Power; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Power utilization is a significant property of a circuit design. System clock signal in electronics product consumes the important part of dynamic power, among them 70% is spent by clock buffers.This critical problem can be optimized using a technique namely clock gating. Here a traditional LFSR is first designed and the output is then compared with LFSR designed using various clock gating techniques. Thus the unnecessary power dissipation in the design can be reduced by disabling the clock signal to flip-flops when the output is same as the input. Due to this reduced switching activity power consumption is also reduced.
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页数：4
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