Instruction randomization self test for processor cores

被引：81

作者：

Batcher, K ^{[1
]}

Papachristou, C ^{[1
]}

机构：

[1] Case Western Reserve Univ, Dept Comp Engn, Cleveland, OH 44106 USA

来源：

17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/VTEST.1999.766644

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Access to embedded processor cores for application of test has greatly complicated the testability of large systems on silicon. Scan based testing methods cannot be applied to processor cores which cannot be modified to meet the design requirements for scan insertion. Instruction Randomization Self Test (IRST) achieves stuck-at-fault coverage for an embedded processor core without the need for scan insertion or mux isolation for application of test patterns. This is a new built-in self test method which combines the execution of microprocessor instructions with a small amount of on-chip test hardware which is used to randomize those instructions. IRST is well suited for meeting the challenges of resting ASIC systems which contain embedded processor cores.

引用

页码：34 / 40

页数：3