Reduce SW/HW migration efforts by a RTOS in multi-FPGA systems

被引:0
|
作者
Zhou, Bo [1 ]
Chen, Yonghui [1 ]
Qiu, Weidong [1 ]
Chen, Yan [1 ]
Peng, Chenglian [1 ]
机构
[1] Fudan Univ, Dept Comp & Informat Technol, Shanghai 200433, Peoples R China
来源
COMPUTER SUPPORTED COOPERATIVE WORK IN DESIGN II | 2006年 / 3865卷
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The boundary between software and hardware is becoming blurry in modern embedded systems, especially in reconfigurable computing systems. It makes an easy-to-use design space explorer more important than ever for engineers. This paper proposes a RTOS (Real-Time Operating System) to reduce design efforts while migrating functions between software and hardware. The RTOS provides reconfigurable hardware threads with identical API inter-faces and data structures, just like those for software threads. To utilize reconfigurable resources efficiently, the states of threads are controlled and managed by the RTOS. Threads can also be preconfigured according to static DFGs (data flow graphs). Experiments on the Rhealstone benchmark have shown that multi-thread environments provided by the proposed RTOS can extend the scale of traditional operating systems and give designers more freedom to perform design space exploration.
引用
收藏
页码:636 / 645
页数:10
相关论文
共 50 条
  • [21] A Multi-Tenant Resource Management System for Multi-FPGA Systems
    Yamakura, Miho
    Takano, Ryousei
    Ben Ahmed, Akram
    Sugaya, Midori
    Amano, Hideharu
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2021, E104D (12): : 2078 - 2088
  • [22] Partitioning and placement for multi-FPGA systems using genetic algorithms
    Hidalgo, JI
    Lanchares, J
    Hermida, R
    PROCEEDINGS OF THE 26TH EUROMICRO CONFERENCE, VOLS I AND II, 2000, : 204 - 211
  • [23] Network-on-Multi-Chip (NoMC) for multi-FPGA multimedia systems
    Stepniewska, Marta
    Luczak, Adam
    Siast, Jakub
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 475 - 481
  • [24] An Efficient Inter-FPGA Routing Exploration Environment for Multi-FPGA Systems
    Farooq, Umer
    Baig, Imran
    Alzahrani, Bander A.
    IEEE ACCESS, 2018, 6 : 56301 - 56310
  • [25] Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems
    Farooq, Umer
    Chotin-Avot, Roselyne
    Azeem, Moazam
    Ravoson, Maminionja
    Turki, Mariem
    Mehrez, Habib
    PROCEEDINGS OF THE 2016 27TH INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP): SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE, 2016, : 107 - 113
  • [26] An Analytical Model for Multilevel Performance Prediction of Multi-FPGA Systems
    Holland, Brian
    George, Alan D.
    Lam, Herman
    Smith, Melissa C.
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2011, 4 (03)
  • [27] Partitioning and placement for multi-FPGA systems using genetic algorithms
    Dpto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, 28040 Madrid, Spain
    Conf. Proc. EUROMICRO, 1600, (204-211):
  • [28] Energy-efficient scheduling on multi-FPGA reconfigurable systems
    Jing, Chao
    Zhu, Yanmin
    Li, Minglu
    MICROPROCESSORS AND MICROSYSTEMS, 2013, 37 (6-7) : 590 - 600
  • [29] SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems
    Zang, Xinshi
    Young, Evangeline F. Y.
    Wong, Martin D. F.
    PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023, 2023, : 593 - 598
  • [30] A circuit partitioning algorithm with replication capability for multi-FPGA systems
    Togawa, N
    Sato, M
    Ohtsuki, T
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1995, E78A (12) : 1765 - 1776