A Low-Jitter Self-Biased Phase-Locked Loop for SerDes

被引：0

作者：

Yuan, Heng-zhou ^{[1
]}

Guo, Yang ^{[1
]}

Liu, Yao ^{[1
]}

Liang, Bin ^{[1
]}

Guo, Qian-cheng ^{[1
]}

Tan, Jia-wei ^{[1
]}

机构：

[1] Natl Univ Def Technol, Coll Comp\, Changsha 410073, Hunan, Peoples R China

来源：

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2016年

基金：

中国国家自然科学基金;

关键词：

PLL; self-biased; low-jitter; serializer-deserializer; PLL;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25 Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential charge pump which has property of low mismatch is proposed. The self biased technology is used to make the bandwidth track the division ratio, which will improve suppression of VCO noise at higher output frequency. The simulation results under 65nm show good jitter performance.

引用

页码：59 / 60

页数：2

共 6 条

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[Anonymous], ISSCC

[2]

[Anonymous], 1983, Signals and Systems

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[4]

FISCHETTE D, 2010, ISSCC, P246

[5]

Loke Alvin L. S., 2006, IEEE J SOLID-ST CIRC, V41, P1894

[6] Low-jitter process-independent DLL and PLL based on self-biased techniques [J].

Maneatis, JG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1723-1732

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