共 38 条
[1]
Statistical timing based optimization using gate sizing
[J].
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS,
2005,
:400-405
[2]
Agarwal A, 2005, DES AUT CON, P321
[3]
Agarwal A, 2003, ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, P900
[4]
[Anonymous], 2010, PREDICTIVE TECHNOLOG
[5]
Bhardwaj S, 2005, DES AUT CON, P541
[6]
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage
[J].
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS,
2006,
:953-958
[9]
Full-chip analysis of leakage power under process variations, including spatial correlations
[J].
42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005,
2005,
:523-528