Three-Dimensional Wafer Scale Integration for Ultra-Large-Scale Cognitive Systems

被引：0

作者：

Wan, Zhe ^{[1
]}

Iyer, Subramanian S. ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Elect & Comp Engn Dept, CHIPS, Los Angeles, CA 90095 USA

来源：

2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2017年

关键词：

system scaling; three-dimensional-wafer-scale-integration; cognitive system;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a method to use three-dimensional wafer scale integration (3D-WSI) to build large-scale cognitive systems up to the scale of a human brain (10(10) neurons, 10(13) synapses). We analyze the effect of scaling by simulating some cognitive systems. The result exhibits attractive properties of the 3D-WSI technology, as compared with the traditional integration scheme using printed circuit boards. At the scale of a human brain, the 3D-WSI system reduces the communication latency by about 10X, while consuming at least 100X less communication power.

引用

页数：2

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