Correcting multiple design errors in digital VLSI circuits

被引：0

作者：

Veneris, AG ^{[1
]}

Hajj, IN ^{[1
]}

机构：

[1] Univ Illinois, Dept Comp Sci, Chicago, IL 60680 USA

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the increase in the complexity of VLSI circuit design, logic design errors can occur during the synthesis process. In this paper we present an efficient test-vector simulation approach for multiple design error diagnosis and correction. We also compare the quality of test vector simulation and BDDs for this problem and show the competitive performance of the former. Experimental results exhibit the robustness of our approach and confirm the theoretical results.

引用

页码：31 / 34

页数：4

共 9 条

[1]

Aas E. J., 1992, Proceedings. Euro ASIC '92 (Cat. No.92TH0442-4), P172, DOI 10.1109/EUASIC.1992.228029

[2] LOGIC DESIGN VERIFICATION VIA TEST-GENERATION [J].