Device Improvement and Circuit Performance Evaluation of complete SiGe Double Gate Tunnel FETs

In recent past extensive simulation work on Tunnel Field Effect Transistors (TFETs) has already been done. However this is limited to device performance analysis. Evaluation of circuit performance is a topic that is very little touched. This is due to the non availability of compact models of TFETs in the commercial simulator. We generate the TFET model by using the model editor in Cadence OrCAD V16.0. In this paper for the first time we perform the circuit analysis of Extended Channel Tunnel Field Effect Transistors (Extended Channel TFETs), we test them over basic digital circuit. Before that we perform device analysis of double gate extended channel TFETs, extended channel has been tried before on SOI TFETs, we try it for the first time on double gate Si1-xGex TFETs. We even look at the effect of introducing Si layer. The performance of this device is compared for different Ge mole fraction and also with MOSFETs.