Scaling and Soft Errors: Moore of the Same for SOI?

被引：11

作者：

Alles, M. L. ^{[1
]}

Ball, D. R. ^{[1
]}

Massengill, L. W. ^{[1
]}

Schrimpf, R. D. ^{[1
]}

Reed, R. A. ^{[1
]}

Bhuva, B. L. ^{[1
]}

机构：

[1] Vanderbilt Univ, Nashville, TN 37203 USA

来源：

2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/SOI.2008.4656328

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：129 / 130

页数：2

共 6 条

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Alles, ML ;

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Schrimpf, RD ;

Warren, KM ;

Weller, RA .

2005 IEEE International SOI Conference, Proceedings, 2005, :191-193

[2]

ALLES ML, SELECTED TO IN PRESS

[3] Charge collection and charge sharing in a 130 nm CMOS technology [J].

Amusan, Oluwole A. ;

Witulski, Arthur F. ;

Massengill, Lloyd W. ;

Bhuva, Bharat L. ;

Fleming, Patrick R. ;

Alles, Michael L. ;

Sternberg, Andrew L. ;

Black, Jeffrey D. ;

Schrimpf, Ronald D. .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) :3253-3258

[4] Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells [J].

Heidel, David F. ;

Rodbell, Kenneth P. ;

Oldiges, Phil ;

Gordon, Michael S. ;

Tang, Henry H. K. ;

Cannon, Ethan H. ;

Plettner, Cristina .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) :3512-3517

[5]

OHKONIN S, 2001, IEEE INT SOI C P, P153

[6] Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design [J].

Olson, BD ;

Ball, DR ;

Warren, KM ;

Massengill, LW ;

Haddad, NF ;

Doyle, SE ;

McMorrow, D .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2132-2136

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