A 0.7V single-supply SRAM with 0-495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

被引：0

作者：

Kushida, Keiichi ^{[1
]}

Suzuki, Azuma ^{[1
]}

Fukano, Gou ^{[1
]}

Kawasumi, Atsushi ^{[1
]}

Hirabayashi, Osamu ^{[1
]}

Takeyama, Yasuhisa ^{[1
]}

Sasaki, Takahiko ^{[1
]}

Katayama, Akira ^{[1
]}

Fujimura, Yuuki ^{[1
]}

Yabe, Tomoaki ^{[1
]}

机构：

[1] Toshiba Co Ltd, Kawasaki, Kanagawa 210, Japan

来源：

2008 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6V. A cascaded bit line scheme saves additional process cost for hierarchical bit tine layer. A test chip with 256kb SRAM utilizing 0.495um(2) cell in 65nm CMOS technology demonstrated 0.7V single supply operation.

引用

页码：37 / 38

页数：2

共 4 条

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