Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

被引：122

作者：

Kao, Kuo-Hsing ^{[1
,2
]}

Verhulst, Anne S. ^{[1
]}

Vandenberghe, William G. ^{[1
,2
]}

Soree, Bart ^{[1
,3
]}

Magnus, Wim ^{[1
,3
]}

Leonelli, Daniele ^{[1
,2
]}

Groeseneken, Guido ^{[1
,2
]}

De Meyer, Kristin ^{[1
,2
]}

机构：

[1] Interuniv Microelect Ctr, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Louvain, Belgium

[3] Univ Antwerp, Dept Phys, B-2020 Antwerp, Belgium

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 08期

关键词：

Fringing field; gate-on-source-only (GoSo); quantum confinement (QC); tunnel field-effect transistor (TFET); vertical tunneling; FIELD-EFFECT TRANSISTORS;

D O I：

10.1109/TED.2012.2200489

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.

引用

页码：2070 / 2077

页数：8

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