A Wide-Range All-Digital Delay-Locked Loop Using Fast-Lock Variable SAR Algorithm

被引：0

作者：

Chen, Wei-Cheng ^{[1
]}

Yang, Rong-Jyi ^{[1
]}

Yao, Chia-Yu ^{[1
]}

Chen, Chao-Chyun ^{[2
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, Dept Elect Engn, Taipei 10607, Taiwan

[2] Yuan Ze Univ, Dept Elect Engn, Taoyuan 32003, Taiwan

来源：

IEEE INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS SYSTEMS (ISPACS 2012) | 2012年

关键词：

Delay-locked Loops; Clock Generators; Binary Search Algorithm;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a wide-operating-range, all digital delay-locked loop (ADDLL) that possesses fast and anti-harmonic lock behavior using a novel fast-lock variable SAR (FVSAR) algorithm. The FVSAR algorithm provides an efficient search sequence for the length-control code of the delay line in the ADDLL. An 11-bit FVSAR ADDLL prototype was fabricated in the TSMC 0.18-mu m CMOS process. The chip's core area is 0.2 mm(2). With 1.6-V supply, the power consumption of the ADDLL chip is less than 10 mW. Compared with the conventional VSAR algorithm, the proposed FVSAR ADDLL reduces the lock time by at least 35% when the input clock frequency is between 66 MHz and 550 MHz.

引用

页数：5

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