Variable-Step 12-bit ADC based on Counter Ramp Recycling Architecture suitable for CMOS Imagers with Column-Parallel Readout

A 12-bit counter ramp recycling analog-to-digital converter (ADC) is proposed, which can be configured in a single-step mode for achieving high conversion accuracy as well as in various multi-step modes for yielding high conversion speed. A unique ADC circuit realization is used for the different modes of operation, while a digital control unit is responsible for providing the necessary control signals to the ADC. Similar to common counter ramp architectures, the proposed implementation is suitable for column-parallel readout owing to its simplicity. The proposed variable-step recycling ADC is implemented in a 0.18 mu m CMOS technology from UMC. Simulation results show good agreement with the expected trade-off between speed and accuracy, which is common to all conventional ADCs.