16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme

被引：18
作者：
Hung, Tsung-Chih [1 ]
Wang, Jia-Ching [1 ]
Kuo, Tai-Haur [1 ]
机构：
[1] Natl Cheng Kung Univ, Tainan, Taiwan
来源：
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC) | 2020年
关键词：
D O I：
10.1109/isscc19947.2020.9063055
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：256 / +
页数：3
相关论文
共 6 条
[1]  
Hershberg B., 2012, 2012 IEEE International Solid-State Circuits Conference (ISSCC), P460, DOI 10.1109/ISSCC.2012.6177090
[2]   A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch [J].
Hung, Tsung-Chih ;
Kuo, Tai-Haur .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (05) :1425-1435
[3]   A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS [J].
Lagos, Jorge ;
Hershberg, Benjamin ;
Martens, Ewout ;
Wambacq, Piet ;
Craninckx, Jan .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (02) :403-416
[4]  
Lim Y, 2017, SYMP VLSI CIRCUITS, pC98, DOI 10.23919/VLSIC.2017.8008562
[5]  
Murmann B., ADC Performance Survey 1997-2024
[6]  
Verbruggen, 2014, IEEE S VLSI CIRC, P1
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