Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process

被引：0
|
作者：
Yeh, Chih-Ting [1 ,2 ]
Ker, Ming-Dou [2 ,3 ]
机构：
[1] Ind Technol Res Inst, Informat & Commun Res Labs, Hsinchu, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect, Dept Elect Engn, Hsinchu, Taiwan
[3] Shou Univ I, Dept Elect Engn, Kaohsiung, Taiwan
来源：
2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2013年
关键词：
Electrostatic discharge (ESD); gate leakage; power-rail ESD clamp circuit; silicon-controlled rectifier (SCR); PROTECTION DESIGN; LATCHUP;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45 mu m can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25 degrees C under the normal circuit operating condition with 1V bias.
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收藏
页数：6
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