8-layers 3D Vertical RRAM with Excellent Scalability towards Storage Class Memory Applications

被引：90

作者：

Luo, Qing ^{[1
,2
]}

Xu, Xiaoxin ^{[1
,2
]}

Gong, Tiancheng ^{[1
,2
]}

Lv, Hangbing ^{[1
,2
]}

Dong, Danian ^{[1
]}

Ma, Haili ^{[1
]}

Yuan, Peng ^{[1
]}

Gao, Jianfeng ^{[1
]}

Liu, Jing ^{[1
]}

Yu, Zhaoan ^{[1
]}

Li, Junfeng ^{[1
]}

Long, Shibing ^{[1
,2
]}

Liu, Qi ^{[1
,2
]}

Liu, Ming ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing, Peoples R China

[2] Univ Chinese Acad Sci, Beijing, Peoples R China

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

基金：

中国国家自然科学基金;

关键词：

D O I：

10.1109/iedm.2017.8268315

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we experimentally demonstrated a bit cost scalable (BiCS) 8-layer 3D vertical RRAM with ultimate scalability. The design of self-selective cell (SSC) with non-filamentary switching were successfully extended to 8 stacks and exhibits salient features, including high nonlinearity (> 10(2)), forming free and high endurance (> 10(7)). An extremely scaled 3D structure with 5 nm size and 4 nm vertical pitch was further demonstrated. The sub mu A operation current is quite promising for low power applications, but not good for sensing speed. A fixed bitline voltage sensing circuit was proposed to address the latency issue. Sub-mu s read latency in bit sensing mode was successfully achieved.

引用

页数：4