A New Low-Power Full-Adder Cell For Low Voltage Using CNTFETs

被引：0

作者：

Jttendra, K. S. ^{[1
]}

Srirtivasulu, Avireni ^{[2
]}

Singh, Brahrnadeo Prasad ^{[1
]}

机构：

[1] Manipal Univ, Dept Elect & Commun Engn, Jaipur 303007, Rajasthan, India

[2] Vignans Univ, VFSTR Univ, Dept Elect & Commun Engn, Vadlamudi 522213, Andhra Pradesh, India

来源：

PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTERS AND ARTIFICIAL INTELLIGENCE - ECAI 2017 | 2017年

关键词：

CNTFET; MOSFET; Full Adder; Low Voltage; Low-Power; Monte Carlo; Ripple Carry Adder; CMOS; DESIGN; LOGIC;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

One of the most crucial components in the computing devices is the full adders. The efficiency and effectiveness of arrays of full adders is essential; thus making it sensible to put in a reasonable effort towards improvisation of computational devices. In this paper, a new 1-BIT Full Adder (FA) with a combination of pass transistor logic and transmission gate logic is suggested. This new hybrid adder is having only 18 transistors. The proposed full adder is a CNTFET based design and also implemented 8-BIT Ripple carry Adder (RCA) at 32 urn CNTFET model files using the Cadence virtuoso tool.

引用

页数：5

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