On-Chip Relative Single-Event Transient/Single-Event Upset Susceptibility Test Circuit for Integrated Circuits Working in Real Time

被引：5
作者：
Hao, Peipei [1 ,2 ]
Chen, Shuming [1 ,2 ]
Wu, Zhenyu [1 ,2 ]
Chi, Yaqing [1 ,2 ]
机构：
[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China
[2] Natl Univ Def Technol, Natl Lab Paralleling & Distributed Proc, Changsha 410073, Hunan, Peoples R China
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2018年 / 65卷 / 01期
基金：
中国国家自然科学基金;
关键词：
Highly reliable integrated circuit; low overhead; relative susceptibility; single-event transient (SET); single-event upset (SEU); test circuit; CMOS TECHNOLOGY; FLIP-FLOP; COMBINATORIAL; DESIGN; AREA; SEU;
D O I：
10.1109/TNS.2017.2784569
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
With technology scaling down, scale of the integrated circuit (IC) increases rapidly. It is unrealistic to harden every element in the IC, hence it is critical to evaluate relative single-event transient (SET) or single-event upset (SEU) sensitivity of each node in the IC to selectively harden the elements connected to the identified highly sensitive nodes. Therefore, this paper proposes a test circuit to measure the relative SET/SEU sensitivity of each node in any circuit working in real time. This will have significant implications for designing ICs with high reliability and low overheads.
引用
收藏
页码：376 / 381
页数：6
相关论文
共 23 条
[1]  
[Anonymous], 2007, INT TECHNOLOGY ROADM
[2]  
[Anonymous], 2014, SINGLE EVENT EFFECTS
[3]   Propagating SET characterization technique for digital CMOS libraries [J].
Baze, M. P. ;
Wert, J. ;
Clement, J. W. ;
Hubert, M. G. ;
Witulski, A. ;
Amusan, O. A. ;
Massengill, L. ;
McMorrow, D. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) :3472-3478
[4]   Digital single event transient trends with technology node scaling [J].
Benedetto, J. M. ;
Eaton, P. H. ;
Mavis, D. G. ;
Gadlage, M. ;
Turflinger, T. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) :3462-3465
[5]   Upset hardened memory design for submicron CMOS technology [J].
Calin, T ;
Nicolaidis, M ;
Velazco, R .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1996, 43 (06) :2874-2878
[6]   Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area [J].
Chen, Shuming ;
Du, Yankang ;
Liu, Biwei ;
Qin, Junrui .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2014, 61 (01) :646-653
[7]   Characterization of Single-Event Transient Pulse Broadening Effect in 65 nm Bulk Inverter Chains Using Heavy Ion Microbeam [J].
Chi, Yaqing ;
Song, Ruiqiang ;
Shi, Shuting ;
Liu, Biwei ;
Cai, Li ;
Hu, Chunmei ;
Guo, Gang .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2017, 64 (01) :119-124
[8]   Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process [J].
Gadlage, MJ ;
Eaton, PH ;
Benedetto, JM ;
Turflinger, TL .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2120-2124
[9]   Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology [J].
Hansen, David L. ;
Miller, Eric J. ;
Kleinosowski, Aj ;
Kohnen, Kirk ;
Le, Anthony ;
Wong, Dick ;
Amador, Karina ;
Baze, Mark ;
DeSalvo, David ;
Dooley, Maryanne ;
Gerst, Kenneth ;
Hughlock, Barrie ;
Jeppson, Bradford ;
Jobe, R. D. ;
Nardi, David ;
Ojalvo, Isabel ;
Rasmussen, Brad ;
Sunderland, David ;
Truong, John ;
Yoo, Michael ;
Zayas, E. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) :3542-3550
[10]   Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology [J].
He Yibai ;
Chen Shuming ;
Chen Jianjun ;
Chi Yaqing ;
Liang Bin ;
Liu Biwei ;
Qin Junrui ;
Du Yankang ;
Huang Pengcheng .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2012, 59 (06) :2772-2777
123