A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

被引:0
作者
Raghavan, Ramprasad [1 ]
Perera, Darshika G. [1 ]
机构
[1] Univ Colorado, Dept Elect & Comp Engn, Colorado Springs, CO 80933 USA
来源
2017 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING (PACRIM) | 2017年
关键词
Big data analysis; parallel processing architecture; FPGAs; K-Means clustering; embedded hardware; hardware algorithms; data mining;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The exponential growth of complex, heterogeneous, dynamic, and unbounded data, generated by a variety of fields including health, genomics, physics, climatology, and social networks pose significant challenges in data processing and desired speed-performance. Existing processor-based software-only algorithms are incapable of analyzing and processing this enormous amount of data, efficiently and effectively. Consequently, some kind of hardware support is desirable to overcome the challenges in analyzing big data. Big data analytics involves many important data mining tasks including clustering, which categorizes the data into meaningful groups based on the similarity or dissimilarity among objects. In this research work, we introduce an efficient FPGA-based parallel processing architecture for K-means Clustering, one of the most popular clustering algorithms. Experiments are performed on a benchmark dataset to evaluate the feasibility and efficiency of our hardware design. Our hardware architecture is generic, parameterized, and scalable to support larger and varying datasets as well as a varying number of clusters. Our hardware configuration with 32 processing elements (PEs) achieved 368 times speedup compared to its software counterpart.
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页数:8
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