Configurable Mapper and Demapper for the Physical Layer of a SDR-Based Wireless Transceiver

In this paper, field programmable gate array (FPGA) implementation of an adaptive constellation mapper and demapper is discussed for use in a SDR-based wireless transceiver. The adaptive functions at the physical layer of wireless technologies play a key role in achieving optimum performance. These functions include forward error correction (FEC) coding, puncturing, orthogonal frequency division multiplexing (OFDM), constellation mapping, sub-channelization, and frame assembly etc. We present here constellation mapping and demapping that supports gray-coded BPSK, QPSK, 16QAM, and 64QAM modulation schemes. This block can be configured at run time so that you can use them in multi-user systems where each user may be operating with a different modulation scheme. The proposed mapper/demapper block is implemented on a Xilinx Virtex-II pro FPGA and it is characterized in terms of functional correctness, area, power, and speed. Experimental results show that our design takes 1360 gates and can run at a maximum frequency of 320 MHz.