Accurate on-chip interconnect evaluation: A time-domain technique

被引：32
|
作者：
Soumyanath, K [1 ]
Borkar, S [1 ]
Zhou, CY [1 ]
Bloechel, BA [1 ]
机构：
[1] Intel Corp, Microcomp Res Lab, Hillsboro, OR 97124 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 05期
关键词：
delay estimation; integrated circuit interconnections; integrated circuit measurements; integrated circuit metallization; integrated circuit modeling; integrated circuit noise; integrated circuits; noise measurement; time-domain measurements;
D O I：
10.1109/4.760372
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 mu m process [1].
引用
收藏
页码：623 / 631
页数：9
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