Design of analog current-mode loser-take-all circuit

被引：4

作者：

Asloni, Mohsen ^{[1
]}

Khoei, Abdollah ^{[1
]}

Hadidi, Khayrollah ^{[1
]}

机构：

[1] Urmia Univ, Dept Elect Engn, Microelect Res Lab, Orumiyeh 57159, Iran

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2006年 / E89C卷 / 06期

关键词：

loser-take-all; winner-take-all;

D O I：

10.1093/ietele/e89-c.6.819

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4 x N MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias affects the threshold voltage of transistors and improves performance of the structure.

引用

页码：819 / 822

页数：4

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