Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

被引：80

作者：

Beckers, Arnout ^{[1
]}

Jazaeri, Farzan ^{[1
]}

Grill, Alexander ^{[2
,3
]}

Narasimhamoorthy, Subramanian ^{[2
]}

Parvais, Bertrand ^{[2
,4
]}

Enz, Christian ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, Integrated Circuits Lab, CH-2000 Neuchatel, Switzerland

[2] IMEC, B-3001 Heverlee, Belgium

[3] Katholieke Univ Leuven, MICAS, Dept Elect Engn ESAT, B-3000 Leuven, Belgium

[4] Vrije Univ Brussel, Dept Elect & Informat, B-1050 Brussels, Belgium

来源：

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2020年 / 8卷

关键词：

Threshold voltage; Cryogenics; Ionization; Temperature dependence; MOSFET; 28-nm bulk CMOS; cryogenic; cryo-CMOS; freezeout; incomplete ionization; interface traps; threshold voltage; FREEZE-OUT; IMPURITY IONIZATION; TRANSISTORS; BEHAVIOR; SEMICONDUCTOR; EXTRACTION;

D O I：

10.1109/JEDS.2020.2989629

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

引用

页码：780 / 788

页数：9

共 44 条

[1] Device modeling at cryogenic temperatures: Effects of incomplete ionization [J].

Akturk, Akin ;

Allnutt, Jeffrey ;

Dilli, Zeynep ;

Goldsman, Neil ;

Peckerar, Martin .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) :2984-2990

[2]

Altermatt PP, 2006, J APPL PHYS, V100, DOI 10.1063/1.2386934

[3]

Arora NarainD., 2012, MOSFET models for VLSI circuit simulation: theory and practice

[4] INFLUENCE OF SUBSTRATE FREEZE-OUT ON THE CHARACTERISTICS OF MOS-TRANSISTORS AT VERY LOW-TEMPERATURES [J].

BALESTRA, F ;

AUDAIRE, L ;

LUCAS, C .

SOLID-STATE ELECTRONICS, 1987, 30 (03) :321-327

[5]

Balestra F, 2001, Device and circuit cryogenic operation for low temperature electronics

[6] Inflection Phenomenon in Cryogenic MOSFET Behavior [J].

Beckers, Arnout ;

Jazaeri, Farzan ;

Enz, Christian .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (03) :1357-1360

[7] Cryogenic MOSFET Threshold Voltage Model [J].

Beckers, Arnout ;

Jazaeri, Farzan ;

Enz, Christian .

49TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2019), 2019, :94-97

[8] Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K [J].

Beckers, Arnout ;

Jazaeri, Farzan ;

Enz, Christian .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01) :1007-1018

[9] Cryogenic MOS Transistor Model [J].

Beckers, Arnout ;

Jazaeri, Farzan ;

Enz, Christian .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (09) :3617-3625

[10] Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing [J].

Beckers, Arnout ;

Jazaeri, Farzan ;

Ruffino, Andrea ;

Bruschini, Claudio ;

Baschirotto, Andrea ;

Enz, Christian .

2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, :62-65

← 1 2 3 4 5 →