Enhanced topology error processing via optimal measurement design

Topology errors constitute one of the significant source of problems for today's state estimators. They may cause significant biases in state estimation solutions and may occasionally lead to divergence of the numerical solution algorithms. Existing methods of detecting and identifying topology errors rely on the measurement residuals which are in turn dependent on the measurement configuration and network topology. Hence, the capability to effectively process topology errors is closely linked to proper measurement design. In particular, detection of a topology error associated with a given branch may or may not be possible depending upon the existing measurement configuration. Hence, it is possible. to efficiently improve the topology error processing capability for a given system by strategically placing few extra measurements. In this paper, a systematic procedure will be developed in order to accomplish this by using not only the traditional power flow and injection measurements but also the newly emerging phasor measurement units (PMUs). Numerical examples will be provided in order to illustrate the proposed measurement placement strategy.