Electrical performance analysis of IC package for the high-end memory device

The developments of processing technology and design make it possible to increase the clock speed and the number of Input Outputs(I/Os) in memory devices. The interconnections of IC(Integrated Circuit) package are considered as an important factor to decide the performance of the memory devices. In order to overcome the limitations of the conventional package, new types of package such as Ball Grid Array(BGA), Chip Scale Package(CSP) or flip chip bonding are adopted by many IC manufacturers. The present work has compared the electrical performances of 3 different packages to provide design guide for IC packages of the high performance memory devices in the future. Those packages are designed for the same memory devices to confront to the diversity of memory market demand. The conventional package using lead frame, wire bonded EGA using Printed Circuit Board (PCB) substrate and flip chip bonded EGA are analyzed. Their electrical performances are compared in the area of signal delay and coupling effect between signal interconnections. The electrical package modeling is built by extracting parasitic of interconnections in IC package through electro-magnetic simulations. The analysis of electrical behavior is performed using SPICE model which is made to represent the real situation. The methodology presented is also capable of determining the most suitable memory package for a particular device based on the electrical performance.