High-speed energy estimation for delay-insensitive circuits

With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. The approach has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys. The method is applied to the NULL Convention Logic (NCL) DI paradigm, and is tested on a number of different NCL multiplier architectures. The results from the developed gate-level switching method are compared to those from transistor-level simulation, showing that the method developed herein produces results more than 1000 times as fast, that fall within the result range obtained by two different industry-standard transistor level simulators, for the tested designs. This method is extremely useful for quickly determining how architecture changes will affect energy usage.