Pipelined Architecture Based Overcurrent Relay on FPGA

Communication between relays and the central control station is an important role in modern power systems. The relays are expected to perform sense-process-communicate cycles. A sequential implementation of these tasks increases the computational time and adversely affects the overall performance of the relay. This paper presents the design and hardware implementation of an overcurrent relay on Field Programmable Gate Array (FPGA) with concurrent pipelined architecture of sense-process-communicate cycles. Harmonics in the system affect the functioning of the relay due to the false tripping. The overcurrent relay employed FFT (Fast Fourier Transform) filter for isolating the fundamental component in the fault current to improve accuracy and avoid false tripping in the design. The relay is implemented on Xilinx Virtex-II Pro XC2VP30-FF896-7C FPGA Board. The proposed relay conforms to IEEE standard C37.112-1996 for overcurrent relays in power systems. It is equipped with serialJIP communication capability. The details of the hardware design, implementation and experimental test results on a hardware simulator of a 360 km transmission line are presented in this paper.