Practical considerations on doughnut transistors design

被引：0

作者：

López, P ^{[1
]}

Oberst, M ^{[1
]}

Neubauer, H ^{[1
]}

Hauer, J ^{[1
]}

Cabello, D ^{[1
]}

机构：

[1] Univ Santiago de Compostela, Dept Elect & Comp Sci, E-15782 Santiago, Spain

来源：

PROCEEDINGS OF THE 2005 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOL 3 | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For applications where speed is important and custom design is an option, doughnut transistors constitute an attractive alternative to standard topologies, efficiently reducing parasitic capacitances while keeping large W/L ratios. This paper explores the influence of the layout style on the chip performance. To this aim a two-stage op-amp where different types of doughnut layouts have been considered for the input differential pair has been constructed and measured. Experimental results suggest better performance for circle-type layouts.

引用

页码：213 / 216

页数：4

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