共 50 条
[41]
VHDL Schematic Design and FPGA Simulation of Neural Network Activation Function using Continued Fractions
[J].
2022 IEEE 13TH ANNUAL UBIQUITOUS COMPUTING, ELECTRONICS & MOBILE COMMUNICATION CONFERENCE (UEMCON),
2022,
:469-474
[42]
A Power Efficient Neural Network Implementation on Heterogeneous FPGA and GPU Devices
[J].
2019 IEEE 20TH INTERNATIONAL CONFERENCE ON INFORMATION REUSE AND INTEGRATION FOR DATA SCIENCE (IRI 2019),
2019,
:193-199
[44]
Efficient FPGA Implementation of a Convolutional Neural Network for Radar Signal Processing
[J].
2021 IEEE 3RD INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS),
2021,
[45]
FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements
[J].
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS),
2018,
[46]
FPGA BASED IMPLEMENTATION OF A FUZZY NEURAL NETWORK MODULAR ARCHITECTURE FOR EMBEDDED SYSTEMS
[J].
2012 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN),
2012,
[48]
Work-in-Progress: Drama: A High Efficient Neural Network Accelerator on FPGA using Dynamic Reconfiguration
[J].
INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE, AND SYNTHESIS FOR EMBEDDED SYSTEMS (CODES +ISSS) 2019,
2019,
[49]
Efficient Hardware Architecture of Softmax Layer in Deep Neural Network
[J].
2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC),
2016,
:323-326
[50]
Design and Implementation of an FPGA-based Real-Time Face Recognition System
[J].
2011 IEEE 19TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM),
2011,
:97-100