Design and Development of Efficient Face Recognition Architecture using Neural Network on FPGA

被引:0
作者
Ahmed, M. Tousif [1 ]
Sinha, Sanjay [1 ]
机构
[1] Xvidia Technol, Bengaluru, India
来源
PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICICCS) | 2018年
关键词
FPGA; Face Recognition System(FRS); Neural Networks (NN); Histogram of Oriented Gradients (HOG);
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Face Recognition is an application used for identification of a person among the pool of images. The main goal is to identify the face among the database of images. As the geometrical features of the face images are similar, distinguishing one face from other faces from the other base is challenging task. The Proposed work uses the Neural Network as classifier using Histogram of Oriented Gradients features of images. The proposed architecture uses Levenberg-Marquardt feed-forward training method for neural network. ORL data base is used and is implemented on VIRTEX-7 FPGA platform giving better recognition rate and high performance.
引用
收藏
页码:905 / 909
页数:5
相关论文
共 50 条
[41]   Designing efficient accelerator of depthwise separable convolutional neural network on FPGA [J].
Ding, Wei ;
Huang, Zeyu ;
Huang, Zunkai ;
Tian, Li ;
Wang, Hui ;
Feng, Songlin .
JOURNAL OF SYSTEMS ARCHITECTURE, 2019, 97 :278-286
[42]   A Power Efficient Neural Network Implementation on Heterogeneous FPGA and GPU Devices [J].
Tu, Yuexuan ;
Sadiq, Saad ;
Tao, Yudong ;
Shyu, Mei-Ling ;
Chen, Shu-Ching .
2019 IEEE 20TH INTERNATIONAL CONFERENCE ON INFORMATION REUSE AND INTEGRATION FOR DATA SCIENCE (IRI 2019), 2019, :193-199
[43]   FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements [J].
Hailesellasie, Muluken ;
Hasan, Syed Rafay ;
Khalid, Faiq ;
Awwad, Falah ;
Shafique, Muhammad .
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[44]   Efficient FPGA Implementation of a Convolutional Neural Network for Radar Signal Processing [J].
Zhang, Jingchi ;
Huang, Yihao ;
Yang, Huanrui ;
Martinez, Michael ;
Hickman, Granger ;
Krolik, Jeffrey ;
Li, Hai .
2021 IEEE 3RD INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS), 2021,
[45]   FPGA BASED IMPLEMENTATION OF A FUZZY NEURAL NETWORK MODULAR ARCHITECTURE FOR EMBEDDED SYSTEMS [J].
Prado, R. N. A. ;
Melo, J. D. ;
Oliveira, J. A. N. ;
Doria Neto, A. D. .
2012 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2012,
[46]   ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems [J].
Nambi, Suresh ;
Ullah, Salim ;
Sahoo, Siva Satyendra ;
Lohana, Aditya ;
Merchant, Farhad ;
Kumar, Akash .
IEEE ACCESS, 2021, 9 :103691-103708
[47]   Work-in-Progress: Drama: A High Efficient Neural Network Accelerator on FPGA using Dynamic Reconfiguration [J].
Yang, Yang ;
Wang, Chao ;
Zhou, Xuehai .
INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE, AND SYNTHESIS FOR EMBEDDED SYSTEMS (CODES +ISSS) 2019, 2019,
[48]   Efficient Hardware Architecture of Softmax Layer in Deep Neural Network [J].
Yuan, Bo .
2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2016, :323-326
[49]   Design and Implementation of an FPGA-based Real-Time Face Recognition System [J].
Matai, Janarbek ;
Irturk, Ali ;
Kastner, Ryan .
2011 IEEE 19TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2011, :97-100
[50]   FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network [J].
Gilan, Ali Azarmi ;
Emad, Mohammad ;
Alizadeh, Bijan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (04) :755-759