A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

被引:60
作者
Hayashi, Isamu [1 ]
Amano, Teruhiko [1 ]
Watanabe, Naoya [1 ]
Yano, Yuji [1 ]
Kuroda, Yasuto [1 ]
Shirata, Masaya [1 ]
Dosaka, Katsumi [1 ]
Nii, Koji [1 ,2 ]
Noda, Hideyuki [1 ]
Kawai, Hiroyuki [1 ]
机构
[1] Renesas Elect Corp, Itami, Hyogo 6640005, Japan
[2] Kanazawa Univ, Kanazawa, Ishikawa 9201192, Japan
关键词
Differential sense amplifier; low-voltage matchline; reference voltage generator; ternary content-addressable memory (TCAM); voltage down converter; TCAM;
D O I
10.1109/JSSC.2013.2274888
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of matchlines to 33% compared with conventional one and realizes 42% fast match-line sensing. At 1.0-V typical supply voltage, 250-MHz search frequency is achieved. The power consumption of fully paralleled search operation at 250 MHz is 9.3 W, which is 66% smaller than previous work. This work has realized high-speed, low-power, and robust large-scale TCAM. We believe that this work will greatly contribute to reducing the power of network systems.
引用
收藏
页码:2671 / 2680
页数:10
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