A Highly Integrable FPGA-Based Runtime-Configurable Multilayer Perceptron

被引：4

作者：

Skodzik, Jan ^{[1
]}

Altmann, Vlado ^{[1
]}

Wagner, Benjamin ^{[1
]}

Danielis, Peter ^{[1
]}

Timmermann, Dirk ^{[1
]}

机构：

[1] Univ Rostock, Inst Appl Microelect & Comp Engn, D-18051 Rostock, Germany

来源：

2013 IEEE 27TH INTERNATIONAL CONFERENCE ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS (AINA) | 2013年

关键词：

Artificial Neural Networks; Multilayer perceptrons; Reconfigurable logic; Runtime; IMPLEMENTATION;

D O I：

10.1109/AINA.2013.19

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a highly integrable Field Programmable Gate Array-based hardware design of multilayer perceptron as a realization of an artificial neural network is presented. Such a hardware solution ensures a deterministic behavior required for any hard real-time compositions. The integration into existing systems is achieved by the application of UDP/IP. Additionally, the presented design is highly flexible due to a parameterizable multilayer perceptron approach. However, most reconfigurations usually require a hard coded reimplementation, resynthesis, and the download of a new bitfile to the target platform, which also requires an additional host PC. Contrary with the presented solution, it is possible to configure the multilayer perceptron's parameters during runtime via a software interface. This approach allows the multilayer perceptron to be adapted to nearly any application. The developed design combines the flexibility of a software solution to generate and comfortably reconfigure the multilayer perceptron as well as the high performance of a hardware solution. As proof of concept, a running prototype has been realized, which shows the design to be highly flexible and with good performance while the hardware resource consumption is kept minimal.

引用

页码：429 / 436

页数：8

共 12 条

[1]

Earl D. D., 2004, THESIS

[2] NeuroFPGA -: Implementing artificial neural networks on programmable logic devices [J].

Ferrer, D ;

González, R ;

Fleitas, R ;

Acle, JP ;

Canetti, R .

DESIGNERS' FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2004, :218-223

[3] Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for Online Applications [J].

Gomperts, Alexander ;

Ukil, Abhisek ;

Zurfluh, Franz .

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, 2011, 7 (01) :78-89

[4]

I. S. Association, 2012, ETH FIELD

[5]

Latif L., 2010, INQUIRER

[6]

Liu JH, 2005, PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON NEURAL NETWORKS AND BRAIN, VOLS 1-3, P915

[7]

Omondi AR, 2006, FPGA IMPLEMENTATIONS OF NEURAL NETWORKS, P1, DOI 10.1007/0-387-28487-7_1

[8] A networked FPGA-based hardware implementation of a neural network application [J].

Restrepo, HF ;

Hoffmann, R ;

Perez-Uribe, A ;

Teuscher, C ;

Sanchez, E .

2000 IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2000, :337-338

[9] THE PERCEPTRON - A PROBABILISTIC MODEL FOR INFORMATION-STORAGE AND ORGANIZATION IN THE BRAIN [J].

ROSENBLATT, F .

PSYCHOLOGICAL REVIEW, 1958, 65 (06) :386-408

[10] LEARNING REPRESENTATIONS BY BACK-PROPAGATING ERRORS [J].

RUMELHART, DE ;

HINTON, GE ;

WILLIAMS, RJ .

NATURE, 1986, 323 (6088) :533-536

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