Design and simulation of modified ultra low power CMOS Comparator for Sigma Delta Modulator

Comparator plays a very important role in most of the analog circuits like ADC and DAC and the performance of these analog circuits is majorly influenced by the choice of the comparator. A low power and high speed comparator is required for high speed Analog to digital converter. In this paper a well defined and improved design of CMOS comparator is presented which is suitable for Ultra Low power Sigma to Delta Converter. The comparator design is a modified design of two stage CMOS op-amp. The proposed comparator is realized using Cadence Virtuoso. Design and Simulation are carried using 180nm CMOS process technology and 1.8 power supply. Input voltage and reference voltage are taken as 1V and 0V respectively for comparison. The results of the proposed comparator are compared with the earlier work done [1], [3], [4] and hence we can clearly see the improvement in power dissipation of the proposed comparator. With the proposed comparator design we achieve ultra low power consumption of 21.16uW